1. Field of the Invention
The present invention generally relates to a protection device and an improvement in device gain for Integrated Circuit (IC) technologies. More particularly, the present invention relates to electrostatic discharge (ESD) protection structures for metal-oxide-semiconductor (MOS) devices and gain improvement for parasitic bipolar devices.
2. Description of the Prior Art
Electrostatic discharge, ESD hereafter, is a common phenomenon that occurs when touching a grounded object with one's fingertips. Highly visible effects, such as sparks, might be seen during an ESD event. The sparks are the result of the ionization of the air-gap between the charged human body and the almost zero-potential surface of the grounded object. Clearly a high voltage discharge takes place under this circumstance. The high voltages result in large electric fields and high current densities in small devices which can lead to the breakdown of insulators and thermal damage in integrated circuits.
In a typical work environment a charge of about 0.6 uC can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4000 volts or greater. Any contact by the charged human body with a grounded object such as an IC pin can result in a discharge for about 100 nanoseconds with peak currents in the ampere range. The energy associated with this discharge could mean failure to electronic devices and components. Typically, the damage is thermally initiated in the form of device or interconnect burnout. The high currents could also lead to on-chip voltages that are high enough to cause oxide breakdown in thin gate MOS processes. ESD protection for semiconductor ICs is, therefore, a reliability issue.
The most fundamental function of an ESD protection transistor is to conduct and draw ESD current away from the circuit it is protecting. Such ESD protection transistors are commonly used on microprocessors, embedded microcontrollers, application-specific integrated circuits and other logic devices, primarily for protection of internal circuits. For example, as shown in FIG. 1, an n-channel thick field-oxide (TFO) transistor generally used as a protection device is depicted. In the drawing, a semiconductor device 10 having a bond pad 11 and an internal circuit 12 to be protected. A line 13 connects the blocks 11 and 12. An n-channel TFO transistor T1 as an ESD protection device is disposed between the line 13 and ground, designated as GND, whereby the gate is tied to the drain and then connected to line 13. The source is connected to the GND voltage. The TFO transistor T1 acts as a parasitic bipolar transistor, and it must turn on before a MOS transistor of the internal circuit 12 reaches its impact ionization breakdown voltage. If the TFO transistor T1 is not designed to turn on first, then the internal circuit 12 will fail an ESD pulse or stress coming from the bond pad 11. Typically, the level of ESD protection will vary as the fabrication process changes due to variations in the on-resistance characteristics of the internal circuit 12. It will be appreciated that the method of the ESD protection transistor being discussed throughout the specification may be employed between bond pads and internal circuits.
A few approaches have been used to improve ESD protection transistors. For example, the use of silicide-blocked source and drain regions has been used to enhance ESD strength but still suffers insufficient ESD protection. Another common method to ensure that the ESD protection transistor turns on first is to increase the channel length of the internal circuit transistors so that they are harder to turn on. However, the current technology in ESD protection MOS transistors uses the ESD implant to dope the source/drain after the contact opens. The main purpose of ESD implant is to increase the impurity concentration and also to make the junction in the Lightly Doped Drain (LDD) regions deeper. The area of the drain region would be larger and wider for ESD implant, resulting in the easy occurrence of punch-through. A longer channel length is required in order to avoid the occurrence of punch-through. Due to the trend of making smaller and tinier semiconductor device sizes, the method of ESD implant and the method of ensuring the ESD protection transistor turns on first are not what is desired. Those two methods would both result in a larger chip area. Although increasing the well doping density for the method of ESD implant can also solve the problem of easily occurring punch-through, the higher the doping the lower the vertical BJT gain. This situation might also restrict the applications of certain electrical circuits.